The present invention relates to the field of liquid crystal display, in particular, to a timing controller and a liquid crystal display comprising the timing controller.
The timing controller (TCON) is a chip in the liquid crystal display (LCD) module, and is used to receive video stream data from a video signal processing device (such as a multimedia processor or an image processor), conduct serial processing on the video stream data and form a drive signal which drives multiple source driver integrated circuits, so that the source driver integrated circuits form different data voltages to drive the display flat panel to display different images.
FIG. 1 is a schematic view of the structure of a liquid crystal display screen in the prior art. As shown in FIG. 1, the timing controller (TCON) is connected with multiple source drive integrated circuits (SDIC). From the structure of the liquid crystal display screen shown in FIG. 1, no any clock transmission line is separately provided in the display screen. That is to say, the timing controller (TCON) in the prior art transmits video stream data and clock signals via a data transmission line.
The data transmission manner of not separately providing a clock transmission line in the prior art achieves more convenient data transmission within the LCD display screen. However, this data transmission design in the prior art requires transmitting clock information via a data channel, which requires that the source drive integrated circuit (IC) should contain a clock-data recovery (CDR) module therein.
In usual circumstances, a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL) is used to implement the clock-data recovery module. Usually, the recovery time (i.e. the locked time) of the clock signal of each PLL or DLL will be recovered in 100 us or longer (which is related to the bandwidth of the PLL or DLL). Thus, compared with the transmission line dedicated for transmitting clock information, using the PLL or DLL to recover the clock signal would require relatively long time, so as to achieve a stable state of the transmission of the clock signal.
Also, if the different display manners of the display screens during practical use are taken into consideration, using the PLL or DLL to recover the clock signal would also require different periods of time. For example, in an sDDRS mode among the display manners of the display screens, as the energy consumption of the display screens is lowered in a manner of reducing update rate, when the clock signal frequencies of the display screens change, the transmission interface between the timing controller and the source drive IC will require a longer locking period of time. In addition, when the display modes of the display screens change, the locking period of time of the timing controller also gets longer. For example, when the display screens transform from a normal display mode to a fail safe mode, the locking period of time will also increase.
FIG. 2 is a schematic view of the structure of the timing controller in the prior art. As shown in FIG. 2, receiving the video stream is realized via the LVDS interface (in specific circuits it may be other interface standards). The video clock signal in the LVDS interface serves as a reference clock of MPLL to generate multiple clocks of different phases. The multiple clocks of multiple phases have two purposes: one is to serve as a high speed sampling clock of the interface to receive the high speed serial video signal of the interface part using an over sampling principle, and the other is to use the clocks of multiple phases as a modulation source of a spread spectrum clock signal. The data part subjected to correct sampling will be stored in a memory, and is usually the effective video data of one video row or multiple video rows. Using the memory to store video data in the timer mainly aims to use the memory to convert data from the video clock domain as received to a clock domain desired by a sending format, and use the memory to convert the data format from a row format as received to a specific format compatible with a drive chip. The clock sign subjected to distributed spectrum clock with spread spectrum via the DSP's modulating and choosing and the DPLL's filtering. The spread spectrum clock subjected to frequency change via a final TXPLL generates a rate desired by the sending format and has a spread spectrum characteristic to drive the final data sending.
As discussed above, to support a distributed spectrum desired by display screens, usually three Locked Loops are required in current timing controllers to generate distributed clock signals, as the reference clocks of all the Locked Loops come from inputted clocks, when inputted clock frequency changes, all Locked Loops need to relock new frequencies. Hence, this structure leads to a long locking period of time of the overall system.
Meanwhile, from the structure of the timing controller shown in FIG. 2, the reference clock signal inputted via the input end of the phase locked loop MPLL is a pixel clock signal sent by a video signal processing device (for example, a media processor or image processor) via a differential signal input unit (the LVDS RX shown in FIG. 2), and the rate at which the timing controller outputs the video stream data will be controlled by the pixel clock signal inputted via the input end of the locked loop MPLL. Different frequency values of the pixel clock signal will result in different locking periods of time of the locked loop within the timing controller, and will also result in change of the bit rate at which the timing control outputs data within the conversion period for outputting the video stream data. Particularly, when the frequency of the reference clock frequency changes or the display mode of the display screen changes, as the locked loop needs to relock at a new frequency, it will take a relatively long period of time to relock the timing controller and the source drive integrated circuit connected with the timing controller so as to adapt to the new frequency, which will prolong the stabilization time of the video stream data during transmission.
To sum up, the locking period of time of the timing controller is long and the rate at which the timing controller outputs the video stream data is affected by input, which are the main disadvantages of the timing controller in a clock-free transmission line in the prior art, and will to a certain extent restrict the use of the timing controller of the clock-free transmission line in the prior art.